`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/12/04 12:16:18
// Design Name: 
// Module Name: bzc
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module bzc
#(parameter data_length=8)
(
    input rst,clk,en,
    input [data_length-1:0] data_in,
    output reg data_out
    );
    
reg [data_length-1:0] data_temp;    
always @(posedge clk) begin
    if (!en) data_out=data_temp[7];
end
always @(posedge clk or posedge en or negedge rst) begin
    if (!rst) data_temp<=0;
    else if (en) data_temp<=data_in;
    else data_temp<=(data_temp<<1);
end
endmodule